Configuring an Embedded Neuromorphic coprocessor using a RISC-V chip for enabling edge computing applications

被引:3
|
作者
Forno, Evelina [1 ]
Spitale, Andrea [1 ]
Macii, Enrico [1 ]
Urgese, Gianvito [1 ]
机构
[1] Politecn Torino, I-10138 Turin, TO, Italy
关键词
D O I
10.1109/MCSoC51149.2021.00055
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Neuromorphic hardware shows promising potential for employment in edge computing applications, as it can provide real-time and low-power elaboration of complex data directly on edge using computational paradigm based on Spiking Neural Networks (SNNs). However, such systems cannot be deployed as edge devices by themselves, as they require an external host for configuration and data input management. In this paper, we present a chip-level integrated system performing on-edge configuration of a neuromorphic platform. The proposed solution makes use of two existing open-source platforms: the low-power RISC-V processor Rocket Chip and the digital SNN processor ODIN. We built the two systems into a single SoC using the Chipyard framework, and connected them by designing a communication interface using ODIN's SPI and AER input/output ports. We validated the system by RTL simulation of a synfire chain running on ODIN, where Rocket Chip sets up configuration of the network, triggers the first spike, then collects the simulation results. The synthesized design utilizes a modest amount of resources on a PYNQ-Z2 board: 16% of LUT slices, 11% of Block RAMs and 8 pins, leaving plenty of room to integrate other peripherals or systems. The present work represents a first step towards seamless integration of neuromorphic technologies with state-of-the-art processors, improving on the ease of use of neuromorphic devices and leading the way into widespread use of SNN coprocessors in edge computing applications.
引用
收藏
页码:328 / 332
页数:5
相关论文
共 26 条
  • [21] Epileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network
    Bahr, Andreas
    Schneider, Matthias
    Francis, Maria
    Lehmann, Hendrik
    Barg, Igor
    Buschhoff, Anna-Sophia
    Wulff, Peer
    Strunskus, Thomas
    Faupel, Franz
    BIOSENSORS-BASEL, 2021, 11 (07):
  • [22] PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters
    Garofalo, Angelo
    Rusci, Manuele
    Conti, Francesco
    Rossi, Davide
    Benini, Luca
    2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2019, : 33 - 36
  • [23] DARKSIDE: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training
    Garofalo, Angelo
    Perotti, Matteo
    Valente, Luca
    Tortorella, Yvan
    Nadalini, Alessandro
    Benini, Luca
    Rossi, Davide
    Conti, Francesco
    ESSCIRC 2022- IEEE 48TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2022, : 273 - 276
  • [24] A RISC-V Neuromorphic Micro-Controller Unit (vMCU) with Event-Based Physical Interface and Computational Memory for Low-Latency Machine Perception and Intelligence at the Edge
    Mendat, Daniel R.
    Sengupta, Jonah P.
    Tognetti, Gaspar
    Villemur, Martin
    Pouliquen, Philippe O.
    Montano, Sergio
    Sanni, Kayode
    Molin, Jamal L.
    Zachariah, Nishant
    Doxas, Isidoros
    Andreou, Andreas G.
    2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS, 2023,
  • [25] Reliability Analysis of Baremetal and FreeRTOS Applications on Microchip PolarFire SoC RISC-V Multiprocessors Using High-Energy Protons
    Mattos, Andre M. P.
    Santos, Douglas A.
    Dilillo, Luigi
    IEEE ACCESS, 2025, 13 : 19922 - 19936
  • [26] Minimizing Latency for 5G Multimedia and V2X Applications using Mobile Edge Computing
    Srinivasa, R. K.
    Naidu, Naveen Kumar Srinivasa
    Maheshwari, Sumit
    Bharathi, C.
    Kumar, Hemanth A. R.
    2019 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT COMMUNICATION AND COMPUTATIONAL TECHNIQUES (ICCT), 2019, : 213 - 217