Analysis and Mitigation of Single-Event Gate Rupture in VDMOS With Termination Structure

被引：10
|
作者：
Chen, Zhuojun [1 ,2 ]
Zhang, Chenchen [1 ,2 ]
Wu, Ming [1 ,2 ]
Wang, Teng [3 ]
Zeng, Yun [1 ,2 ]
Wan, Xin [4 ,5 ]
Jin, Hu [4 ,5 ]
Xu, Jun [4 ]
Tang, Minghua [6 ]
机构：
[1] Hunan Univ, Key Lab Micro Nano Optoelect Devices, Minist Educ, Changsha 410082, Peoples R China
[2] Hunan Univ, Sch Phys & Elect, Hunan Prov Key Lab Lowdimens Struct Phys & Device, Changsha 410082, Peoples R China
[3] Shanghai Inst Space Power Sources, Shanghai 201100, Peoples R China
[4] Tsinghua Univ, Ctr High Reliabil Power Semicond, Yangtze Delta Reg Inst, Hangzhou 314000, Zhejiang, Peoples R China
[5] Aurorachip Co Ltd, Hangzhou 314000, Zhejiang, Peoples R China
[6] Xiangtan Univ, Sch Mat Sci & Engn, Xiangtan 411105, Peoples R China
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2021年 / 68卷 / 06期
基金：
中国国家自然科学基金;
关键词：
Logic gates; Ions; Electric fields; Electric breakdown; Voltage measurement; Transistors; Silicon; Electric field; heavy ion; radiation hardness; single-event gate rupture (SEGR); vertical double-diffused MOSFET (VDMOS); SIC POWER MOSFETS; ION ENERGY; SEGR; IMPACT;
D O I：
10.1109/TNS.2021.3077244
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
During heavy-ion experiments, the single-event gate rupture (SEGR) effects can still be observed in the vertical double-diffused power MOSFET (VDMOS) with radiation-hardened cells. Fault analysis demonstrates that the hot spots locate at the termination of the VDMOS. Then, several mitigation solutions for termination structure are discussed comprehensively by means of TCAD simulations. Finally, a combined hardness method with horizontally extending P+ region and adding floating N+ region is proposed. It is effective to reduce the electric field of gate oxide to below the calculated critical field, without additional masks and process steps.
引用
收藏
页码：1272 / 1278
页数：7
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