A Multi-chip SiP Package Design Scheme

被引：0

作者：

Cai, Tiantian ^{[1
]}

Xi, Wei ^{[1
]}

Suo, Siliang ^{[1
]}

Jian, Ganyang ^{[1
]}

Yao, Hao ^{[1
]}

Yu, Zhengqiang ^{[2
]}

机构：

[1] CSG, Elect Power Res Inst, Guangzhou 510663, Guangdong, Peoples R China

[2] Beijing Smart Chip Microelect Technol Co Ltd, Beijing Engn Res Ctr High Reliabil IC Power Ind G, Beijing 100192, Peoples R China

来源：

PROCEEDINGS OF 2019 IEEE 8TH JOINT INTERNATIONAL INFORMATION TECHNOLOGY AND ARTIFICIAL INTELLIGENCE CONFERENCE (ITAIC 2019) | 2019年

关键词：

SiP package; Chip stack; Substrate design; SiP simulation;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The structure design scheme of two-chip stack, chip and device is adopted in this design, and the main control chip, the safety chip and several kinds of passive components are designed and assembled on the multi-layer substrate by using the SiP package. When the PAD to PAD bonding mode is not suitable, the corresponding PAD of the two chips can be led out to the different fingers of the substrate, and then the method of interconnection of the different finger on the substrate is performed. The design process of SiP package substrate and the items needing attention are described. The rationality of this design is proved by the simulation results of power supply, signal and heat dissipation performance.

引用

页码：1889 / 1893

页数：5

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