Testing configurable LUT-based FPGAs

A novel approach to testing lookup table (LUT) based field programmable gate arrays (FPGAs) is proposed in this paper. A general structure for the basic configurable logic array blocks (CLBs) is assumed. We group k CLBs in the column into a cell, where k denotes the number of inputs or an LUT. The whole chip is configured as a group of one-dimensional iterative logic allays of cells. We assume that in each linear cell array, there is at most one faulty cell, and that multiple faulty CLBs in the same cell can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable/reconfigurable arrays are also derived. Our idea is to configure the cells so as to make each cell function bijective. This property is helpful for applying pseudoexhaustive test patterns to each cell and propagating errors to the observable outputs. In order to detect all the faults defined, k + 2 configurations are required, and the resulting number of test patterns is 2(k). A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k + 4. Our BIST approaches also have the advantage of requiring fewer hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, three lest sessions are required. However, the maximum number of configurations for diagnosing a faulty CLB is k + 4.