Device footprint scaling for ultra thin body fully depleted SOI

被引：0

作者：

Deng, Jie ^{[1
]}

Kim, Keunwoo ^{[2
]}

Chuang, Ching-Te ^{[2
]}

Wong, H. -S Philip ^{[1
]}

机构：

[1] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

[2] IBM T J Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier.

引用

页码：145 / +

页数：2

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