Efficient hardware implementation for H.264/AVC motion estimation

Variable block size motion estimation (VBSME) is adopted in H.264/AVC to improve the coding efficiency. However, supporting various block sizes significantly increases the complexity of both video encoding and decoding. In this paper a multi-level parallel architecture for H.264/AVC motion estimation is proposed. A SIMD architecture is proposed for absolute differentiator and accumulator (ADA). Using the ADA as the main processing engine, a cost and performance SAD processor is proposed. Experimental results indicate that more than 100% performance improvement is achieved by the proposed architectures compared to the state-of-the-art architectures with similar resources.