Low-complexity bit-parallel systolic multipliers over GF(2m)

被引：3
|
作者：
Chiou-Yng Lee
Chin-Chin Chen
Yuan-Ho Chen
Erl-Huei Lu
机构：
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON SYSTEMS, MAN, AND CYBERNETICS, VOLS 1-6, PROCEEDINGS | 2006年
关键词：
systolic array; folded technique; primitive polynomial; interleaved conventional multiplication;
D O I：
10.1109/ICSMC.2006.384557
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2(m)) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithms permit efficient realization of the bit-parallel multiplication using iterative arrays. The results show that our proposed time-dependent and time-independent multipliers save about 38% and 54% space complexity as compared to the traditional multipliers, respectively.
引用
收藏
页码：1160 / 1165
页数：6
相关论文
共 50 条
  • [41] Transition fault testability in bit parallel multipliers over GF(2m)
    Rahaman, H.
    Mathew, J.
    Sikdar, B. K.
    Pradhan, D. K.
    25TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2007, : 422 - +
  • [42] Transition faults detection in bit parallel multipliers over GF(2m)
    Bengal Engineering and Science University, Shibpur Howrah-711103, India
    不详
    不详
    WSEAS Trans. Circuits Syst., 2008, 12 (1049-1059): : 1049 - 1059
  • [43] Single error correctable bit parallel multipliers over GF(2m)
    Mathew, J.
    Jabir, A. M.
    Rahaman, H.
    Pradhan, D. K.
    IET COMPUTERS AND DIGITAL TECHNIQUES, 2009, 3 (03): : 281 - 288
  • [44] C-testable bit parallel multipliers over GF(2m)
    Rahaman, H.
    Mathew, J.
    Pradhan, D. K.
    Jabir, A. M.
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2008, 13 (01)
  • [45] Low-complexity Parallel and Serial Systolic Architectures for AB2 Multiplication in GF(2m)
    Kim, Kee-Won
    Lee, Won-Jin
    IETE TECHNICAL REVIEW, 2013, 30 (02) : 134 - 141
  • [46] Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2m)
    Chiou-Yng Lee
    Che Wun Chiou
    Jim-Min Lin
    Journal of Electronic Testing, 2005, 21 : 539 - 549
  • [47] Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m)
    Lee, CY
    Chiou, C
    Lin, JM
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2005, 21 (05): : 539 - 549
  • [48] Low-Power and Low-Hardware Bit-Parallel Polynomial Basis Systolic Multiplier over GF(2m) for Irreducible Polynomials
    Mathe, Sudha Ellison
    Boppana, Lakshmi
    ETRI JOURNAL, 2017, 39 (04) : 570 - 581
  • [49] Low-complexity systolic multiplier over GF(2m) using weakly dual basis
    Lee, CY
    Lu, YC
    Lu, EH
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS, 2002, : 367 - 372
  • [50] Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2m)
    Shao, Qiliang
    Hu, Zhenji
    Basha, Shaik Nazeem
    Zhang, Zhiping
    Wu, Zhiqiang
    Lee, Chiou-Yng
    Xie, Jiafeng
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2018, 65 (08) : 2455 - 2465
12345