FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel Method

被引：2

作者：

Fox, Sean ^{[1
]}

Boland, David ^{[1
]}

Leong, Philip ^{[1
]}

机构：

[1] Univ Sydney, Sydney, NSW, Australia

来源：

PROCEEDINGS OF THE 2018 ACM/SIGDA INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS (FPGA'18) | 2018年

基金：

澳大利亚研究理事会;

关键词：

D O I：

10.1145/3174243.3174271

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper, we describe a systolic Field Programmable Gate Array (FPGA) implementation of the Fastfood algorithm that is optimised to run at a high frequency. The Fastfood algorithm supports online learning for large scale kernel methods. Empirical results show that 500 MHz clock rates can be sustained for an architecture that can solve problems with input dimensions that are 10(3) times larger than previously reported. Unlike many recent deep learning publications, this design implements both training and prediction. This enables the use of kernel methods in applications requiring a rare combination of capacity, adaption and speed.

引用

页码：279 / 284

页数：6

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