Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

被引：2
|
作者：
Blaho, M
Pogany, D
Gornik, E
Denison, M
Groos, G
Stecher, M
机构：
[1] Vienna Univ Technol, Inst Solid State Elect, A-1040 Vienna, Austria
[2] Infineon Technol, D-81617 Munich, Germany
来源：
MICROELECTRONICS RELIABILITY | 2003年 / 43卷 / 04期
关键词：
D O I：
10.1016/S0026-2714(03)00021-0
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics. (C) 2003 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：545 / 548
页数：4
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