A Review on SRAM Memory Design Using FinFET Technology

被引:1
|
作者
Lakshmi, T. Venkata [1 ]
Kamaraju, M. [2 ]
机构
[1] Gudlavalleru Engn Coll, Vijayawada, Andhra Pradesh, India
[2] Gudlavalleru Engn Coll, Dept Elect & Commun Engn, AS&A, Vijayawada, Andhra Pradesh, India
关键词
CMOS; FinFET; Short Channel Effect; SRAM; Static Noise Margin; LOW-POWER; DEVICES; SYSTEM; IMPACT; ENERGY; CELL;
D O I
10.4018/IJSDA.302665
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
An innovative technology named FinFET (fin field effect transistor) has been developed to offer better transistor circuit design and to compensate the necessity of superior storage system (SS). As gate loses control over the channel, CMOS devices face some major issues like increase in manufacturing cost, less reliability and yield, increase of ON current, short channel effects (SCEs), increase in leakage currents, etc. However, it is necessary for the memory to have less power dissipation, short access time, and low leakage current. The traditional design of SRAM (static RAM) using CMOS technology represents severe performance degradation due to its higher power dissipation and leakage current. Thus, a nano-scaled device named FinFET is introduced for designing SRAM since it has threedimensional design of the gate. FinFET has been used to improve the overall performance and has been chosen as a transistor of choice because it is not affected by SCEs. In this work, the researchers have reviewed various FinFET-based SRAM cells, performance metrics, and the comparison over different technologies.
引用
收藏
页数:21
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