An Optimized ΔΣ Fractional-N Frequency Synthesizer for CMOS UHF RFID Reader

被引：0
|
作者：
Shi, Chunqi [1 ]
Zhang, Runxi [1 ]
Lai, Zongsheng [1 ]
机构：
[1] E China Normal Univ, Inst Microelect Circuits & Syst, Shanghai 200062, Peoples R China
来源：
2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2009年
关键词：
CMOS; delta-sigma(Delta Sigma); fractional-N synthesizer; ultra-high-frequency radio-frequency identification (UHF RFID); TRANSCEIVER; TECHNOLOGY;
D O I：
10.1109/ASICON.2009.5351343
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel 3-bit 3rd-order Delta Sigma fractional-N frequency synthesizer specialized for monolithic UHF band radio frequency identification reader is implemented in 0.18 mu m CMOS technology. The phase noise requirements are recapitulated for the zero-IF transceiver architecture and EPC global CIG2 and ETSI multi-protocol operation. The measurement results show that the synthesizer phase noise at 200 kHz offset is suppressed by the additional zero configuration in delta-sigma modulator (DSM)'s noise transfer function with acceptable in-band noise penalty. The measured phase noise is -102 and -126.5dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz operation frequency while drawing 9.6 mA from 1.8 V power supply.(1)
引用
收藏
页码：545 / 548
页数：4
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