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- [43] Simulation of 100nm SOI MOSFET with FINFET structure SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 883 - 886
- [44] Solutions for printing sub 100nm contacts with ArF OPTICAL MICROLITHOGRAPHY XV, PTS 1 AND 2, 2002, 4691 : 503 - 514
- [45] ArF lithography for the 130 and 100nm technology nodes MICROPROCESSES AND NANOTECHNOLOGY 2000, DIGEST OF PAPERS, 2000, : 6 - 7
- [46] A simulation evaluation of 100nm CMOS device performance SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 2001, 2001, : 288 - 291
- [48] Challenge and innovation of VLSI design below 100nm 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test (VLSI-TSA-DAT), Proceedings of Technical Papers, 2005, : 144 - 144
- [49] Influences on accuracy of SEM based CD mask metrology with a view to the 32 nm node EMLC 2008: 24TH EUROPEAN MASK AND LITHOGRAPHY CONFERENCE, 2008, 6792
- [50] Full-chip application for SRAM gate at 100nm node and beyond using chromeless phase lithography 23RD ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2003, 5256 : 112 - 121