A low power implementation for the motion estimation processor

被引：0
|
作者：
Jou, JM [1 ]
Shiau, YH [1 ]
Zheng, BR [1 ]
机构：
[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan
来源：
2002 IEEE REGION 10 CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND POWER ENGINEERING, VOLS I-III, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a low power, Video Motion Estimation processor. The combination of motion fuzzy prediction and modified four-step algorithm (4SS) gives faster and more correct searching results. With the analysis of the relationship between the consecutive search iterations, sonic of the searching operation are saved which enhance the computing efficiency and reduce power consumption. Experimental results demonstrate the higher performance in both PNSR and computation complexity then other systems.
引用
收藏
页码：220 / 223
页数：4
相关论文
共 50 条
  • [1] A low-power video motion estimation array processor
    Yeh, GK
    Lu, YW
    Burr, JB
    1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, : 162 - 163
  • [2] A low power block-matching analog motion estimation processor
    Panovic, M
    Demosthenous, A
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4827 - 4830
  • [3] A low-power analog motion estimation processor for digital video coding
    Panovic, M
    Demosthenous, A
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (03) : 673 - 683
  • [4] An ultra-low complexity motion estimation algorithm and its implementation of specific processor
    Hiratsuka, Seiichiro
    Goto, Satoshi
    Ikenaga, Takeshi
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 4691 - 4694
  • [5] Implementation of a low power motion detection camera processor using a CMOS image sensor
    Lee, SH
    Kim, SW
    Kim, S
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 737 - 740
  • [6] Low-Power Motion Estimation Processor with 3D Stacked Memory
    Zhang, Shuping
    Zhou, Jinjia
    Zhou, Dajiang
    Kimura, Shinji
    Goto, Satoshi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2015, E98A (07) : 1431 - 1441
  • [7] Low-power systolic array processor architecture for FSBM video motion estimation
    Jiang, M.
    Crookes, D.
    Davidson, S.
    Turner, R.
    ELECTRONICS LETTERS, 2006, 42 (20) : 1146 - 1148
  • [8] An ultra low power motion estimation processor for MPEG2 HDTV resolution video
    Miyama, M
    Tooyama, O
    Takamatsu, N
    Kodake, T
    Nakamura, K
    Kato, A
    Miyakoshi, J
    Imamura, K
    Hashimoto, H
    Komatsu, S
    Yagi, M
    Morimoto, M
    Taki, K
    Yoshimoto, M
    IEICE TRANSACTIONS ON ELECTRONICS, 2003, E86C (04) : 561 - 569
  • [9] Power estimation starategies for a low-power security processor
    Lee, Yen-Fong
    Huang, Shi-Yu
    Hsu, Sheng-Yu
    Chen, I-Ling
    Shieh, Cheng-Tao
    Lin, Jian-Cheng
    Chang, Shih-Chieh
    ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, : 367 - 371
  • [10] Design and implementation of low-power motion estimation based on modified full-search block motion estimation
    Basha, S. Mahaboob
    Kannan, M.
    JOURNAL OF COMPUTATIONAL SCIENCE, 2017, 21 : 327 - 332
12345