An FPGA implementation of the LMS adaptive filter for audio processing

This paper proposes three different architectures for implementing a least mean square (LMS) adaptive filtering algorithm, using a 16 bit fixed-point arithmetic representation. These architectures are implemented using the Xilinx multimedia board as an audio processing system. The on-board AC97 audio codec is used for audio capture/playback, and the Virtex-II FPGA chip is used to implement the three architectures. A comparison is then made between the three alternative architectures with different filter lengths for performance and area. Results obtained show an improvement by 90% in the critical part of the algorithm when a hardware accelerator is used to perform it over a pure software implementation. This results in a total speed up of 3.86 x. However using a pure hardware implementation results in a much higher performance with somewhat lower flexibility. It shows a speed up close to 82.6 x over the software implementation.