Advances on Doping Strategies for Triple-Gate FinFETs and Lateral Gate-All-Around Nanowire FETs and Their Impact on Device Performance (vol 62, pg 2, 2017)

被引：0
|
作者：
Veloso, A. [1 ]
De Keersgieter, A. [1 ]
Matagne, P. [1 ]
Horiguchi, N. [1 ]
Collaert, N. [1 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
来源：
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING | 2017年 / 63卷
关键词：
D O I：
10.1016/j.mssp.2017.03.013
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：303 / 303
页数：1
相关论文
共 36 条
  • [31] Device Design for Gate-All-Around-Nanowire Tunneling CMOS-FETs of Axial Ge-Si Heterojunction Through Inverter Performance Evaluation
    Huang, Shengxi
    Wang, Z.
    Zhang, Jinyu
    Guan, Ximeng
    Yuan, Ze
    Moroz, Victor
    Wang, Yan
    Yu, Zhiping
    JOURNAL OF COMPUTATIONAL AND THEORETICAL NANOSCIENCE, 2012, 9 (04) : 510 - 515
  • [32] Design and investigation of doping-less gate-all-around TFET with Mg2Si source material for low power and enhanced performance applications
    Agarwal, Pranav
    Rai, Sankalp
    Rakshit, Y. A.
    Mishra, Varun
    CHINESE PHYSICS B, 2023, 32 (10)
  • [33] Design and investigation of doping-less gate-all-around TFET with Mg2Si source material for low power and enhanced performance applications
    Pranav Agarwal
    Sankalp Rai
    Rakshit Y.A
    Varun Mishra
    Chinese Physics B, 2023, 32 (10) : 705 - 714
  • [34] Asymetrically Strained High Performance Germanium Gate-all-around Nanowire p-FETs featuring 3.5 nm Wire Width and Contractible Phase Change Liner Stressor (Ge2Sb2Te5)
    Cheng, Ran
    Liu, Bin
    Guo, Pengfei
    Yang, Yue
    Zhou, Qian
    Gong, Xiao
    Dong, Yuan
    Tong, Yi
    Bourdelle, Konstantin
    Daval, Nicolas
    Delprat, Daniel
    Nguyen, Bich-Yen
    Augendre, Emmanuel
    Yeo, Yee-Chia
    2013 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2013,
  • [35] A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
    Ram, Mamidala Saketh
    Persson, Karl-Magnus
    Wernersson, Lars-Erik
    2022 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2022,
  • [36] Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free Process
    Lee, Shen-Yang
    Chen, Han-Wei
    Shen, Chiuan-Huei
    Kuo, Po-Yi
    Chung, Chun-Chih
    Huang, Yu-En
    Chen, Hsin-Yu
    Chao, Tien-Sheng
    2019 SILICON NANOELECTRONICS WORKSHOP (SNW), 2019, : 97 - 98
1234