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- [22] Design and implementation of low-power digit-serial multipliers INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 186 - 195
- [25] Energy Reduction of Ultra-Low Voltage VLSI Circuits by Digit-Serial Architectures 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 3012 - 3017
- [26] Design of fast digit-serial adders using SFQ logic circuits IEICE ELECTRONICS EXPRESS, 2009, 6 (19): : 1408 - 1413
- [27] Design space exploration of division over GF(2m) on FPGA:: A digit-serial approach 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 172 - 175
- [28] Digit-serial multiplier design using skew-tolerant domino circuits 14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 356 - 360
- [29] A novel approach to the design and implementation of very high-speed digit-serial modified-Booth multipliers PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 61 - 64
- [30] DESIGN ISSUES IN DIGIT SERIAL SIGNAL PROCESSORS 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 441 - 444