A 1.3GHz 350mW Hybrid Direct Digital Frequency Synthesizer in 90nm CMOS

被引：0

作者：

Yeoh, Hong Chang ^{[1
]}

Jung, Jae-Hun ^{[1
]}

Jung, Yun-Hwan ^{[1
]}

Baek, Kwang-Hyun ^{[1
]}

机构：

[1] Chung Ang Univ, Sch Elect & Elect Engn, Seoul 156756, South Korea

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low power hybrid direct digital frequency synthesizer (DDFS) with a maximum operating frequency of 1.3GHz fabricated in 90nm CMOS. The proposed hybrid design extends the resolution of the nonlinear DAC by adding a linear slope component to the sine approximation via an additional linear DAC. With an 11-bit combined DAC, this DDFS produces a minimum SFDR of 52dBc up to Nyquist at 1.3GHz while dissipating only 350mW and occupying 2mm(2) including pads. The FOM of this chip is measured at 1207.9GHz.2(ENOB)/W.

引用

页码：122 / 123

页数：2

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