Resilient Synchronization of Grid Converters at Low Sampling Frequencies

The phase-locked loop (PLL) is a critical component for synchronization of power converters to the grid. To improve positive sequence detection during non-ideal operating conditions including grid faults, high-voltage unbalance, high-frequency harmonics, and DC offsets, the introduction of harmonic decoupling networks (DN) as PLL pre-filters has been proposed in the literature. These DNs exhibit satisfactory performance at high sampling frequencies (i.e., 10 kHz and above). In some applications such as medium-voltage converters, low sampling/control frequency is necessary, and available harmonic decoupling solutions do not perform satisfactorily. Delay-compensated decoupling networks (DCDN) are proposed in this paper, which, in combination with a linear PLL (L-PLL), exhibit excellent performance improvement at low sampling frequencies. Both simulation and experimental results are presented to verify the effectiveness of the proposed DCDN combined with an L-PLL.