A 2.5-2.6 dB Noise Figure LNA for 39 GHz band in 22 nm FD-SOI with Back-Gate Bias Tunability

被引:0
|
作者
Nyssens, L. [1 ]
Rack, M. [1 ]
Wane, S. [2 ]
Schwan, C. [3 ]
Lehmann, S. [3 ]
Zhao, Z. [3 ]
Lucci, L. [4 ]
Lugo-Alvarez, J. [4 ]
Gaillard, F. [4 ]
Raskin, J-P [1 ]
Lederer, D. [1 ]
机构
[1] Catholic Univ Louvain, Louvain La Neuve, Belgium
[2] eV Technol, Colombelles, France
[3] GlobalFoundries, Dresden, Germany
[4] Univ Grenoble Alpes, CEA Leti, Grenoble, France
关键词
Low-noise amplifier; FD-SOI CMOS; millimeter-wave; Back-gate bias; 5G; spiral inductor;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a 2-stage low-noise amplifier (LNA) designed in 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology, covering the N259 and N260 millimeter-wave 5G bands. The prototype features 19.9 dB peak gain, 2.5-2.6 dB noise figure (NF) and 6.6 GHz bandwidth (intersection of 3 dB gain flatness and -10 dB input/output matching), -5.4 dBm third-order input intercept point (IIP3) for a 20.8 mW power dissipation. Modulating the back-gate bias of each stage independently switches the LNA operation mode from a combination of low-noise (0.8 dB variation in NF), high-linearity (similar to 3 dB variation in IIP3) and/or low-power (down to 7.4 mW). Finally, a careful noise contribution analysis of the input matching identifies a 0.58 dB main contribution from the input spiral inductor. EM simulations show that a 0.06 dB improvement in NF can be achieved by using a high-resistivity substrate, if the input inductor design is optimized by stacking several metal layers.
引用
收藏
页码:60 / 63
页数:4
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