Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

被引：0

作者：

Azais, Florence ^{[1
]}

David-Grignot, Stephane ^{[1
,2
]}

Latorre, Laurent ^{[1
]}

Lefevre, Francois ^{[2
]}

机构：

[1] Univ Montpellier, CNRS, LIRMM, 161 Rue Ada, F-34095 Montpellier, France

[2] NXP Semicond, 2 Espl Anton Phillips, F-14000 Caen, France

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2016年 / 25卷 / 03期

关键词：

Noise measurement; phase noise; analog/IF signals; 1-bit acquisition; digital signal processing; built-in-self-test; BIST; test cost reduction;

D O I：

10.1142/S0218126616400144

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1-bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885 mu m(2), which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

引用

页数：18

共 50 条

[41] On-chip power noise reduction techniques in high performance SoC-based integrated circuits
Popovich, M
Friedman, EG
Secareanu, R
Harlin, OL
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2005, : 309 - 312
[42] Delay uncertainty due to on-chip simultaneous switching noise in high performance cmos integrated circuits
Tang, KT
Friedman, EG
2000 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 2000, : 633 - 642
[43] Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
Yoshikawa, Kumpei
Sasaki, Yuta
Ichikawa, Kouji
Saito, Yoshiyuki
Nagata, Makoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2012, E95A (12) : 2284 - 2291
[44] Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits
Samori C.
IEEE Solid-State Circuits Magazine, 2016, 8 (04): : 81 - 91
[45] Fully integrated low phase-noise VCOs with on-chip MEMS inductors
Park, EC
Choi, YS
Yoon, JB
Hong, S
Yoon, E
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2003, 51 (01) : 289 - 296
[46] On-Chip Investigation of Phase Noise in Monolithically Integrated Gain-Switched Lasers
Alexander, Justin K.
Morrissey, Padraic E.
Caro, Ludovic
Dernaika, Mohamad
Kelly, Niall P.
Peters, Frank H.
IEEE PHOTONICS TECHNOLOGY LETTERS, 2017, 29 (09) : 731 - 734
[47] CAD-oriented equivalent circuit modeling of on-chip interconnects for RF integrated circuits in CMOS technology
Zheng, J
Hahm, YC
Weisshaar, A
Tripathi, VK
1999 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-4, 1999, : 35 - 38
[48] Testing of RF Differential Low Noise Amplifiers using Built-In-Test circuits
Kaviyarasan, J.
Suvitha, S.
INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2012, 12 (04): : 132 - 136
[49] Multifunctional Equipment and Test Results for Total Ionizing Dose Testing of Analog Integrated Circuits
Bakerenkov, Alexander S.
Chubunov, Pavel A.
Anashin, Vasily S.
Rodin, Alexander S.
Felitsyn, Vladislav A.
2016 IEEE RADIATION EFFECTS DATA WORKSHOP (REDW), 2016, : 88 - 91
[50] A Low Power and Low Noise On-Chip Active RF Tracking Filter for Digital TV Tuner ICs
Sun, Yang
Jeong, Chang-Jin
Lee, In-Young
Lee, Sang-Gug
IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (10): : 1698 - 1701

← 1 2 3 4 5 →