Performance Enhancement of a Hybrid 1-bit Full Adder Circuit

被引：0

作者：

Chauhan, Sugandha ^{[1
]}

Sharma, Tripti ^{[1
]}

机构：

[1] Chandigarh Univ, Dept ECE, Gharuan, Punjab, India

来源：

PROCEEDINGS OF THE FIRST IEEE INTERNATIONAL CONFERENCE ON POWER ELECTRONICS, INTELLIGENT CONTROL AND ENERGY SYSTEMS (ICPEICES 2016) | 2016年

关键词：

Hybrid Full Adder; Power Consumption; Delay and PDP;

D O I：

暂无

中图分类号：

TE [石油、天然气工业]; TK [能源与动力工程];

学科分类号：

0807 ; 0820 ;

摘要：

Full adder is a crucial requirement for designing many types of processors like microprocessors, digital signal processors, image processing and various VLSI applications etc. In most of the design adder connected on most critical path of the circuit which affects the overall performance of the system. This paper proposes modified hybrid full adder circuit that enhances the performance in terms of power consumption at various voltages, temperature and operating frequency. It also improves noise immunity by 2-5% than its peer design. All simulations have been performed at 45nm process technology on Tanner EDA tool.

引用

页数：4

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