BitPruner: Network Pruning for Bit-serial Accelerators

被引:21
|
作者
Zhao, Xiandong [1 ,2 ]
Wang, Ying [1 ,2 ,3 ]
Liu, Cheng [1 ]
Shi, Cong [4 ]
Tu, Kaijie [1 ]
Zhang, Lei [1 ]
机构
[1] Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China
[2] Univ Chinese Acad Sci, Beijing, Peoples R China
[3] State Key Lab Comp Architecture, Beijing, Peoples R China
[4] Chongqing Univ, Chongqing, Peoples R China
基金
中国国家自然科学基金;
关键词
neural network; bit-serial accelerator; bit-pruning;
D O I
10.1109/dac18072.2020.9218534
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Bit-serial architectures (BSAs) are becoming increasingly popular in low power neural network processor (NNP) design. However, the performance and efficiency of state-of-the-art BSA NNPs are heavily depending on the distribution of ineffectual weight-hits of the running neural network. To boost the efficiency of third-party BSA accelerators, this work presents Bit-Pruner, a software approach to learn BSA-favored neural networks without resorting to hardware modifications. The techniques proposed in this work not only progressively prune but also structure the non-zero bits in weights, so that the number of zero-hits in the model can be increased and also load balanced to suit the architecture of the target BSA accelerators. According to our experiments on a set of representative neural networks, Bit-Pruner increases the hit-sparsity up to 94.4% with negligible accuracy degradation. When the bit-pruned models are deployed onto typical BSA accelerators, the average performance is 2.1X and 1.5X higher than the baselines running non-pruned and weight-pruned networks, respectively.
引用
收藏
页数:6
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