Automated throughput-driven synthesis of bus-based communication architectures

被引：3

作者：

Pasricha, Sudeep ^{[1
]}

Dutt, Nikil ^{[1
]}

Ben-Romdhane, Mohamed ^{[1
]}

机构：

[1] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92717 USA

来源：

ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2005年

关键词：

D O I：

10.1145/1120725.1120920

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As System-on-Chip (SoC) designs become more complex, it becomes increasingly harder to design communication architectures which satisfy design constraints. Manually traversing the vast communication design space for constraint-driven synthesis is not feasible anymore. In this paper we propose an approach that automates the synthesis of bus-based communication architectures for systems characterized by (possibly several) throughput constraints. Our approach accurately and effectively prunes the large communication design space to synthesize a feasible low-cost bus architecture which satisfies the constraints in a design.

引用

页码：495 / 498

页数：4

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