Fabrication of Suspended Ge-rich Nanowires by Ge Enrichment Technique for Multi-channel Devices

被引：4

作者：

Saracco, E. ^{[1
]}

Damlencourt, J. F. ^{[1
]}

Lafond, D. ^{[1
]}

Bernasconi, S. ^{[2
]}

Benevent, V. ^{[1
]}

Rivallin, P. ^{[1
]}

Morand, Y. ^{[2
]}

Hartmann, J. M. ^{[1
]}

Gautier, P. ^{[1
]}

Vizioz, C. ^{[1
]}

Ernst, T. ^{[1
]}

Bonafos, C. ^{[3
]}

Fazzini, P. ^{[3
]}

机构：

[1] CEA LETI Minatec, 17 Ave Martyrs, F-38054 Grenoble 9, France

[2] STMicroelect, F-38926 Crolles, France

[3] Univ Toulouse, CNRS, CEMES, F-31055 Toulouse 4, France

来源：

ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT | 2009年 / 19卷 / 01期

关键词：

SIGE; SILICON;

D O I：

10.1149/1.3118946

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

This paper presents a new top-down method to fabricate Ge-rich nanowires for multi-channel devices by Ge enrichment technology. 3 dimensional Ge nanowire stacks have been fabricated and characterized by SEM, TEM, EDX. Nanowires obtained are single crystalline with no crystalline defects observed on cross-sectional TEM pictures. The main advantage of this method is that the shape, the size and the concentration of Ge nanowires can be tuned by process parameters. Indeed, depending on these parameters, nanowires with a Ge content up to 100% can be obtained with a very aggressive diameter (as low as 10nm). Moreover, this technology allows the co-integration of Ge and Si nanowires for pMOS and nMOS devices, respectively.

引用

页码：207 / +

页数：2

共 36 条

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