Design of Advanced 2D and 3D FPGAs: Architecture-Level Exploration and Algorithm-Level Optimization

Field Programmable Gate Arrays (FPGAs) have become popular media for the implementation of many digital circuits. The quality of FPGA device is controlled by three factors which are: quality of the FPGA architecture, quality of the Computer-Aided Design (CAD) tools used to map circuits into the FPGA and electrical design of the FPGA. The subject of this paper is the exploration and optimization of cluster-based mesh FPGAs. To conduct this objective, we propose an exploration environment for cluster-based mesh FPGA architectures to explore and improve power consumption, area and performance. We propose also a new 2D cluster-based mesh FPGA architecture using hierarchical interconnect topology and long routing wires. With experimental method, we explore the effect of architecture parameters that control the interconnect flexibility. Results show that long routing wires improve the FPGA flexibility and performance. Nevertheless, as the long wires span increases, their delay also increases and impedes the overall performances. To mitigate the long wire length issues and improve performances, we propose to explore a development methodology of stacked FPGA architecture using 3D technology process. By adjusting the span of long wires, we can design two-tiers 3D cluster-based FPGA with 2 identical 2D functional layers. Moreover, we propose to investigate CAD algorithms aspect to optimize the mapping of application on the 3D FPGA architecture.