Low Trap Density in InAs/High-k Nanowire Gate Stacks with Optimized Growth and Doping Conditions

In this paper, we correlate the growth of InAs nanowires with the detailed interface trap density (D-it) profile of the vertical wrap-gated InAs/high-k nanowire semiconductor-dielectric gate stack. We also perform the first detailed characterization and optimization of the influence of the in situ doping supplied during the nanowire epitaxial growth on the sequential transistor gate stack quality. Results show that the intrinsic nanowire channels have a significant reduction in D-it as compared to planar references. It is also found that introducing tetraethyltin (TESn) doping during nanowire growth severely degrades the D-it profile. By adopting a high temperature, low V/III ratio tailored growth scheme, the influence of doping is minimized. Finally, characterization using a unique frequency behavior of the nanowire capacitance-voltage (C-V) characteristics reveals a change of the dopant incorporation mechanism as the growth condition is changed.