Optimization of Program and Erase Characteristics of Two Bit Flash Memory P-Channel Cell Structure using TCAD

被引:0
|
作者
Hayashi, Hirokazu [1 ]
Axelrad, Valery [2 ]
Mochizuki, Marie [1 ]
Hayashi, Takahisa [1 ]
Maruyama, Tetsuhiro [1 ]
Suzuki, Kazuya [1 ]
Nagatomo, Yoshiki [1 ]
机构
[1] LAPIS Semicond Co Ltd, Device Technol Dev Div, Kouhoku Ku, Yokohama, Kanagawa 2228575, Japan
[2] SEQUOIA Design Syst Inc, Woodside, CA 94062 USA
关键词
Flash Memory; SONOS; Two-Bit; P-Channel; TCAD;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the optimization of the two bit flash memory P-channel cell structure using efficient 2D write and erase model. Our proposed cell structure stores charge at either Source and/or Drain sides of the gate in an SiN film and is based on method of programming by DAHE and erasing by FN tunneling. It is found that expansion of cell window and the improvement of erase characteristic depend on the optimization of the gate-film overlap under gate of the SiN film.
引用
收藏
页码:169 / 172
页数:4
相关论文
共 38 条
  • [1] New erase characteristics for a two-bit SONOS flash memory
    An, HM
    Han, TH
    Seo, KY
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 2003, 43 (05) : 868 - 872
  • [2] Bipolar transistor selected P-channel flash memory cell technology
    Ohnakado, T
    Ajika, N
    Satoh, S
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (05) : 863 - 867
  • [3] 5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells
    Han, Kyoung-Rok
    Jeong, Min-Kyu
    Cho, Ilwhan
    Lee, Jong-Ho
    CURRENT APPLIED PHYSICS, 2010, 10 (01) : E2 - E4
  • [4] A novel gate-injection program/erase p-channel NAND-type flash memory with high (10 m cycle) endurance
    Lue, Hang-Ting
    Lai, Erh-Kun
    Wang, Szu-Yu
    Yang, Ling-Wu
    Yang, Tahone
    Chen, Kuang-Chao
    Hsieh, Kuang-Yeu
    Liu, Rich
    Lu, Chih-Yuan
    2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 140 - +
  • [5] A low-voltage flash memory cell utilizing the gate-injection program/erase method with a recessed channel structure
    Wu, Dake
    Huang, Ru
    Wang, Pengfei
    Tang, Poren
    Wang, Yangyuan
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2008, 23 (07)
  • [6] A novel Uniform-Channel-Program-Erase (UCPE) flash EEPROM using an isolated P-well structure
    Li, CNB
    Farenc, D
    Singh, R
    Yater, J
    Liu, S
    Chang, CL
    Bagchi, S
    Chen, K
    Ingersoll, P
    Chang, KT
    INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 779 - 782
  • [7] TCAD Simulation Study of Two Bit Storage Flash Memory using Conventional FinFET and Junctionless FET
    Srinivasan, R.
    Ambika, R.
    2012 IEEE INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2012, : 92 - 95
  • [8] Multi-Bit/Cell SONOS Flash Memory with Recessed Channel Structure
    Han, Kyoung-Rok
    Kwon, Hyuck-In
    Lee, Jong-Ho
    NSTI NANOTECH 2008, VOL 3, TECHNICAL PROCEEDINGS: MICROSYSTEMS, PHOTONICS, SENSORS, FLUIDICS, MODELING, AND SIMULATION, 2008, : 69 - +
  • [9] Two-Bit/cell characteristics of silicon-oxide-nitride-oxide-silicon flash memory devices with recessed channel structure
    Han, Kyoung-Rok
    Lee, Jong-Ho
    Japanese Journal of Applied Physics, 2008, 47 (4 PART 2): : 2687 - 2691
  • [10] Two-bit/cell characteristics of silicon-oxide-nitride-oxide-silicon flash memory devices with recessed channel structure
    Han, Kyoung-Rok
    Lee, Jong-Ho
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2008, 47 (04) : 2687 - 2691