A fast and accurate delay dependent method for switching estimation of large combinational circuits

被引:2
|
作者
Theoharis, S
Theodoridis, G
Soudris, D [1 ]
Goutis, C
Thanailakis, A
机构
[1] Democritus Univ Thrace, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, GR-67100 Xanthi, Greece
[2] Univ Patras, Dept Elect & Comp Engn, VLSI Design & Testing Ctr, Rion 26110, Greece
[3] ALMA Technol, Pikermi Attika 19009, Greece
关键词
gate level; power estimation; CMOS circuit; low power design; computer aided design;
D O I
10.1016/S1383-7621(02)00120-0
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Assuming inertial gate delay model, the first-order temporal correlation and the structural dependencies, a probabilistic method to estimate the switching activity of a combinational circuit, is introduced. To capture the first temporal correlation a novel mathematical model and the associated new formulas are derived. Also, a modified boolean function, which describes the logic and timing behavior of each signal, is introduced. To capture the structural dependencies an efficient new method to partition a large circuit into small independent sub-circuits is proposed. Finally, an algorithm that evaluates the switching activity of any circuit node is presented. (C) 2002 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:113 / 124
页数:12
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