Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications

被引：0

作者：

Huang, Teng-Chieh ^{[1
]}

Huang, Po-Tsang ^{[1
]}

Wu, Shang-Lin ^{[1
]}

Chen, Kuan-Neng

Chiou, Jin-Chern ^{[1
]}

Chen, Kuo-Hua

Chiu, Chi-Tsung ^{[2
]}

Tong, Ho-Ming ^{[2
]}

Chuang, Ching-Te ^{[1
]}

Hwang, Wei ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Eng, Hsinchu, Taiwan

[2] Adv Semicond Engn ASE, Kaohsiung, Taiwan

来源：

2013 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, an area-power-efficient 11-bit hybrid analog-to-digital converter (ADC) with delay-line enhanced tuning for neural sensing applications is presented. To reduce the total amount of capacitance, this hybrid ADC is composed of a coarse tune and a fine tune by 3-bit delay-lined-based ADC and 8-bit successive approximation register (SAR) ADC, respectively. The delay-lined-based ADC is designed to detect the three most significant bits by a modified vernier structure. To relax the accuracy requirement of the coarse tune, the lifting-based searching algorithm and re-comparison procedure are proposed for the fine tune. To further achieve energy saving, split capacitor array and self-timed control are utilized in the SAR ADC. Fabricated in TSMC 0.18 mu m CMOS technology, an ENOB of 10.4-bit at 8KS/s can be achieved with only 0.6 mu W power consumption and 0.032-mm(2) area. The FoM of this ADC is 49.4fJ/conversion-step.

引用

页码：238 / 241

页数：4

共 28 条

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