A Low-Power Handheld GPU using Logarithmic Arithmetic and Triple DVFS Power Domains

被引:0
|
作者
Nam, Byeong-Gyu [1 ]
Lee, Jeabin [1 ]
Kim, Kwanho [1 ]
Lee, Seung Jin [1 ]
Yoo, Hoi-Jun [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Dept EECS, Taejon 305701, South Korea
关键词
GPU; Hardware Architecture; 3D Computer Graphics; Handheld Systems; Low-Power;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, a low-power GPU architecture is described for the handheld systems with limited power and area budgets. The GPU is designed using logarithmic arithmetic for power- and area-efficient design. For this GPU, a multifunction unit is proposed based on the hybrid number system of floating-point and logarithmic numbers and the matrix, vector, and elementary functions are unified into a single arithmetic unit. It achieves the single-cycle throughput for all these functions, except for the matrix-vector multiplication with 2-cycle throughput. The vertex shader using this function unit as its main datapath shows 49.3% cycle count reduction compared with the latest work for OpenGL transformation and lighting (TnL) kernel. The rendering engine uses also the logarithmic arithmetic for implementing the divisions in pipeline stages. The GPU is divided into triple dynamic voltage and frequency scaling power domains to minimize the power consumption at a given performance level. It shows a performance of 5.26Mvertices/s at 200MHz for the OpenGL TnL and 52.4mW power consumption at 60fps. It achieves 2.47 times performance improvement while reducing 50.5% power and 38.4% area consumption compared with the latest work.
引用
收藏
页码:73 / 80
页数:8
相关论文
共 50 条
  • [1] A low-power vector processor using logarithmic arithmetic for handheld 3D graphics systems
    Nam, Byeong-Gyu
    Yoo, Hoi-Jun
    ESSCIRC 2007: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2007, : 232 - 235
  • [2] Logarithmic number system for low-power arithmetic
    Paliouras, V
    Stouraitis, T
    INTEGRATED CIRCUIT DESIGN, PROCEEDINGS: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2000, 1918 : 285 - 294
  • [3] Logarithmic Arithmetic for Low-Power Adaptive Control Systems
    Uroš Lotrič
    Patricio Bulić
    Circuits, Systems, and Signal Processing, 2017, 36 : 3564 - 3584
  • [4] Logarithmic Arithmetic for Low-Power Adaptive Control Systems
    Lotri, Uro
    Bulic, Patricio
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2017, 36 (09) : 3564 - 3584
  • [5] Using signed digit arithmetic for low-power multiplication
    Crookes, D.
    Jiang, M.
    ELECTRONICS LETTERS, 2007, 43 (11) : 613 - 614
  • [6] Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications
    Ellaithy, Dina M.
    El-Moursy, Magdy A.
    Ibrahim, Ghada H.
    Zaki, Amal
    Zekry, Abdelhalim
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (07) : 2144 - 2152
  • [7] Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels
    Wang, Weihuano
    Choi, Gwan
    Gunnam, Kiran K.
    22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2009, : 51 - +
  • [8] A low-power unified arithmetic unit for programmable handheld 3-D graphics systems
    Nam, Byeong-Gyu
    Kim, Hyejung
    Yoo, Hoi-Jun
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (08) : 1767 - 1778
  • [9] A low-power unified arithmetic unit for programmable handheld 3-D graphics systems
    Nam, Byeong-Gyu
    Kim, Hyejung
    Yoo, Hoi-Jun
    PROCEEDINGS OF THE IEEE 2006 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2006, : 535 - 538
  • [10] Low-power FIR digital filters using residue arithmetic
    Freking, WL
    Parhi, KK
    THIRTY-FIRST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 739 - 743