High-Speed Graphene Based Quantum-Optical Interconnect Design

While traditional transistor scaling in integrated circuit industry is going on one side, interconnect scaling has become the performance-limiting factor for new designs on the other side. The increasing influence of interconnect parasites on crosstalk noise and RLC delay as well as electro-migration and power dissipation concerns have stimulated the introduction of low-resistivity copper and low-permittivity (k) dielectrics to provide performance and reliability enhancement. Additionally, entirely new technology such as optical interconnect is required to address future global routing needs and sustain performance improvement.