Design of a transmission gate based CMOL memory array

被引：1

作者：

Abid, Z. ^{[1
]}

Barua, M. ^{[1
]}

Alma'aitah, A. ^{[1
]}

机构：

[1] Univ Western Ontario, Dept Elect & Comp Engn, London, ON, Canada

来源：

MICRO & NANO LETTERS | 2008年 / 3卷 / 03期

基金：

加拿大自然科学与工程研究理事会;

关键词：

D O I：

10.1049/mnl:20080012

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

A design of a nanoelectronic memory array, compatible with both the molecular switch (nanodevice) electrical characteristics and CMOS 45 nm semiconductor technology node is presented. The proposed transmission gate based CMOL (hybrid CMOS/MOLecular) memory cell does not suffer from the operational difficulties faced by the conventional CMOL cell. The control circuitry with improved multiplexer designs is introduced, and it shows that the required voltage levels to program the nanodevices can be achieved. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cell allowing easier implementation of both logic and memory circuits on the same chip.

引用

页码：70 / 76

页数：7

共 50 条

[41] Design and demonstration of an optical field programmable gate array
Mal, P
Cantin, JF
Beyette, FR
WAVE OPTICS AND VLSI PHOTONIC DEVICES FOR INFORMATION PROCESSING, 2001, 4435 : 238 - 246
[42] GATE-ARRAY DESIGN - A HIERARCHICAL DEVELOPMENT TREND
STANSBERRY, MC
ELECTRONICS AND POWER, 1985, 31 (07): : 519 - 522
[43] AUTOMATION ADVANCES FOR CMOS GATE-ARRAY DESIGN
SCHMITT, EJ
SKORUP, GE
ELECTRONIC DESIGN, 1982, 30 (25) : 155 - &
[44] DESIGN AND APPLICATION OF A 20K GATE ARRAY
HOLZAPFEL, HP
HORNINGER, KH
MICHEL, P
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 1986, 33 (04) : 388 - 393
[45] Design of gate array circuits using evolutionary algorithms
Bungert, Peter
Mostaghim, Sanaz
Schmeck, Hartmut
Branke, Juergen
ARCHITECTURE OF COMPUTING SYSTEMS - ARCS 2008, PROCEEDINGS, 2008, 4934 : 38 - 50
[46] INTELLIGENT LAYOUT TOOLS SIMPLIFY GATE ARRAY DESIGN
GOERING, R
COMPUTER DESIGN, 1987, 26 (09): : 46 - 48
[47] The design of a SRAM-based field-programmable gate array -: Part II:: Circuit design and layout
Chow, P
Seo, SO
Rose, J
Chung, K
Páez-Monzón, G
Rahardja, I
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (03) : 321 - 330
[48] Design exploration of IGZO diode based VCMA array design for Storage Class Memory Applications
Gupta, M.
Perumkunnil, M.
Fantini, A.
Chamazcoti, S. A.
Kim, W.
Bardon, M. G.
Kar, G. S.
Furnemont, A.
ESSDERC 2022 - IEEE 52ND EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2022, : 241 - 244
[49] A 10K-GATE CMOS GATE ARRAY BASED ON A GATE ISOLATION STRUCTURE
SAKASHITA, K
UEDA, M
ARAKAWA, T
ASAI, S
FUJIMURA, T
OHKURA, I
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (01) : 413 - 417
[50] A 10K-GATE CMOS GATE ARRAY BASED ON A GATE ISOLATION STRUCTURE
SAKASHITA, K
UEDA, M
ARAKAWA, T
ASAI, S
FUJIMURA, T
OHKURA, I
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 493 - 497

← 1 2 3 4 5 →