Hierarchical test generation for combinational circuits with real defects coverage

被引：7
|
作者：
Cibáková, T
Fischerová, M
Gramatová, E
Kuzmicz, W
Pleskauz, WA
Raik, J
Ubar, R
机构：
[1] Inst Informat SAS, Bratislava 84237, Slovakia
[2] Inst Electr Mat Technol, PL-02668 Warsaw, Poland
[3] Warsaw Univ Technol, PL-00662 Warsaw, Poland
[4] Tallinn Univ Technol, EE-12618 Tallinn, Estonia
来源：
MICROELECTRONICS RELIABILITY | 2002年 / 42卷 / 07期
关键词：
D O I：
10.1016/S0026-2714(02)00080-X
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper deals with the automatic test pattern generation (ATPG) technique at the higher level using a functional fault model and defect-fault relationship in the form of a defect coverage table at the lower level. The paper contributes to test pattern generation (TPG) techniques taking into account physical defect localisation. A new parameter-probabilistic effectiveness of input patterns-has been used in the TPG technique with the goal of increasing real defect coverage. This parameter is based on probabilities of physical defects in digital cells which may occur in real integrated circuits. This improvement has been implemented into the existing DefGen ATPG system for combinational circuits. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：1141 / 1149
页数：9
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