3D-Sorter: 3D design of a Resource-aware Hardware Sorter for Edge Computing Platforms under Area and Energy consumption constraints

In this paper, we proposed a 3-dimensional hardware sorting architecture (3D-Sorter), based on Multi-Dimensional Sorting Algorithm (MDSA). the proposed architecture transforms a sequence of input records into a 3-dimensional matrix. Records of every dimension are sorted in several MDSA phases, using partial sorting methods. Our synthesis results, provided by Xilinx Vivado indicate that the 3D-Sorter design decreases the number of Look-Up Tables (LUT) and registers by 54% and 42.7%, compared to the state-of-the-art hardware sorter. Also, the power consumption is reduced by 48.15% on average. The results show that the proposed architecture is a remarkable power/area saving for edge components.