Stability Analysis & Design of Hysteretic Current-mode Switched-inductor Buck DC-DC Converters

被引:0
|
作者
Solis, Carlos J. [1 ]
Rincon-Mora, Gabriel A. [1 ]
机构
[1] Georgia Inst Technol, Atlanta, GA 30332 USA
关键词
Hysteretic current-mode control; design; analysis; dc-dc switching converter; stability; high bandwidth; SIGNAL; CONTROLLERS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Battery-supplied systems demand fast, power efficient, and compact power supplies. Although linear regulators are quick and small, tiny batteries cannot sustain their losses for long. Pulse-width-modulated (PWM) switchers are considerably more efficient, but also slower. Luckily, hysteretic converters can respond within one switching cycle. Stabilizing the system for maximum speed with a hysteretic inductor-current loop, however, which is not linear, is not straightforward. This paper shows how load dumps delay the response of the hysteretic oscillator that the current loop implements. Knowing the worse-case dump and the delay it causes reveals the lowest output capacitance that maintains stable operation at maximum speed. The converter designed here can therefore recover, as predicted, from 100-mA load dumps in 2 mu s with 10 mu F and 45 degrees of phase margin.
引用
收藏
页码:811 / 814
页数:4
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