Charge Trapping Analysis of Metal/Al2O3/SiO2/Si, Gate Stack for Emerging Embedded Memories

For Al2O3 charge trapping analysis, Metal/Al2O3/SiO2/Si (MAOS) structures are fabricated from atomic layer deposition and plasma enhanced chemical vapor deposition-based Al2O3 and SiO2 thin films, respectively. The fabricated MAOS devices showed high memory window of similar to 7.81V@16V sweep voltage and leakage current density of similar to 3.88 x 10(-6) A/cm(2)@-1V. The charge trapping and decay mechanism are investigated with the variation of alumina thickness by Kelvin probe force microscopy (KPFM). It reveals that vertical charge decay is a dominant phenomenon of charge loss for Al2O3 in contrast to lateral charge spreading. Constant current stress (CCS) measurements mark the location of charge trap centroid at similar to 10.30 nm from metal/Al2O3 interface attributes that bulk traps present close to the Al2O3/SiO2 interface are dominant charge trap centres. In addition, a simple method is proposed to estimate the trap density using KPFM and CCS method at room temperature. Furthermore, there is similar to 28% exponential decay in high state capacitance observed after 10(4) s in capacitance-time analysis at room temperature. This material engineering of charge traps will improve the performance and functionality of bilayer Al2O3/SiO2 structure for embedded memory applications.