Bi-directional data flow architecture for padding in MPEG-4

被引:0
|
作者
Chandrsekhar, L [1 ]
Vaithianathan, K
Ramaswamy, K
Panchanathan, S
机构
[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85281 USA
[2] Arizona State Univ, Dept Comp Sci & Engn, Tempe, AZ 85281 USA
来源
MEDIA PROCESSORS 2000 | 2000年 / 3970卷
关键词
ISO; MPEG-4; padding; VLSI; motion estimation; VHDL; video processing; content based image and video coding;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The advent of MPEG-4 standard for manipulation and coding of multimedia data has resulted in the exploration of new algorithms and architectural solutions for object and content-based processing. MPEG-4 operates at the level of Video Object Planes (VOP's) in contrast to frame-based processing in MPEG 1 and 2. The motion estimation process in MPEG-4 requires both 8 x 8 and 16 x 16 block motion processing. In addition, a new approach termed padding is employed to improve the accuracy of motion estimation/compensation. We have recently presented a scalable architecture for estimating the motion of both 8 x 8 and 16 x 16 blocks. In this paper, we present a novel architecture for padding in MPEG-4. Padding is carried out for the boundary macroblocks of the VOPs in two steps, namely horizontal padding and vertical padding. Padding is based on the shape information of the individual video objects. The asynchronous communication in the proposed architecture enables high throughput while maintaining a low complexity. The architecture is simple, modular and scalable and has been simulated using VHDL.
引用
收藏
页码:161 / 166
页数:6
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