A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture

An Efficient and flexible implementation of block ciphers is critical to achieve information security processing. Existing implementation methods such as GPP, FPGA and cryptographic application-specific ASIC provide the broad range of support. However, these methods could not achieve a good tradeoff between high-speed processing and flexibility. In this paper, we present a reconfigurable VLIW processor architecture targeted at block cipher processing, analyze basic operations and storage characteristics, and propose the multi-cluster register-file structure for block ciphers. As for the same operation element of block ciphers, we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme. The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations, but also realizes dynamic configuration for cryptographic processing units. It has been implemented with 0.18 mu m CMOS technology, the test results show that the frequency can reach 350MHz, and power consumption is 420mw. Ten kinds of block and hash ciphers were realized in the processor. The encryption throughput of AES, DES, IDEA, and SHA-1 algorithm is 1554Mbps, 448Mbps, 785Mbps, and 424Mbps respectively, the test result shows that our processor's encryption performance is significantly higher than other designs.