Explicit drain current model of junctionless double-gate field-effect transistors

被引:14
|
作者
Yesayan, Ashkhen [1 ]
Pregaldiny, Fabien [2 ]
Sallese, Jean-Michel [3 ]
机构
[1] Armenian Natl Acad Sci, Inst Radiophys & Elect, Ashtarak 0203, Armenia
[2] ICube Telecom Phys Strasbourg, F-67412 Illkirch Graffenstaden, France
[3] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland
基金
瑞士国家科学基金会;
关键词
JLFET; MOS devices; Compact modeling; Silicon devices;
D O I
10.1016/j.sse.2013.07.015
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of applied terminal voltages and structural parameters. The model is validated with 2D numerical simulations for a large range of channel thicknesses and is found to be very accurate for doping densities exceeding 10(18) cm(-3), which are actually used for such devices. (C) 2013 Elsevier Ltd. All rights reserved.
引用
收藏
页码:134 / 138
页数:5
相关论文
共 50 条
  • [21] An explicit surface potential, capacitance and drain current model for double-gate TFET
    Kaur, Sarabjeet
    Raman, Ashish
    Sarin, Rakesh Kumar
    SUPERLATTICES AND MICROSTRUCTURES, 2020, 140
  • [22] Oscillation of gate leakage current in double-gate metal-oxide-semiconductor field-effect transistors
    Do, V. Nam
    Dollfus, P.
    JOURNAL OF APPLIED PHYSICS, 2007, 101 (07)
  • [23] Modelling of the nanoscale channel length effect on the subthreshold characteristics of junctionless field-effect transistors with a symmetric double-gate structure
    Jin, Xiaoshi
    Liu, Xi
    Wu, Meile
    Chuai, Rongyan
    Lee, Jung-Hee
    Lee, Jong-Ho
    JOURNAL OF PHYSICS D-APPLIED PHYSICS, 2012, 45 (37)
  • [24] Drain current model for double-gate tunnel field-effect transistor with hetero-gate-dielectric and source-pocket
    Wang, Ping
    Zhuang, YiQi
    Li, Cong
    Jiang, Zhi
    Liu, YuQi
    MICROELECTRONICS RELIABILITY, 2016, 59 : 30 - 36
  • [25] Short Channel Continuous Model for Double-Gate Junctionless Transistors
    Paz, Bruna Cardoso
    Pavanello, Marcelo Antonio
    Avila, Fernando
    Cerdeira, Antonio
    2014 INTERNATIONAL CARIBBEAN CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICCDCS), 2014,
  • [26] A computational study of short-channel effects in double-gate junctionless graphene nanoribbon field-effect transistors
    Tamersit, Khalil
    JOURNAL OF COMPUTATIONAL ELECTRONICS, 2019, 18 (04) : 1214 - 1221
  • [27] Role of the extensions in Double-Gate Junctionless MOSFETs in the drain current at high gate voltage
    Cerdeira, Antonio
    Avila Herrera, Fernando
    Paz, Bruna Cardoso
    Estrada, Magali
    Pavanello, Marcelo Antonio
    2015 30TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), 2015,
  • [28] Hole Mobility Model for Si Double-Gate Junctionless Transistors
    Chen, Fan
    Wei, Kangliang
    Sha, Wei E. I.
    Huang, Jun Z.
    2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
  • [29] Compact core model for Symmetric Double-Gate Junctionless Transistors
    Cerdeira, A.
    Avila, F.
    Iniguez, B.
    de Souza, M.
    Pavanello, M. A.
    Estrada, M.
    SOLID-STATE ELECTRONICS, 2014, 94 : 91 - 97
  • [30] Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field
    Kim, Sangwan
    Choi, Woo Young
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2017, 56 (08)