A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution

被引：108
|
作者：
Patón, S
Di Giandomenico, A
Hernandez, L
Wiesbauer, A
Pötscher, T
Clara, M
机构：
[1] Univ Carlos III Madrid, E-28911 Madrid, Spain
[2] Infineon Technol Austria, A-9500 Villach, Austria
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 07期
关键词：
analog-digital conversion; continuous-time filters; delta-sigma modulation; low-pass filters; low-voltage design; sigma-delta modulation;
D O I：
10.1109/JSSC.2004.829925
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-mum CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.
引用
收藏
页码：1056 / 1063
页数：8
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