A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS

被引：4

作者：

Di Giandomenico, A ^{[1
]}

Paton, S ^{[1
]}

Wiesbauer, A ^{[1
]}

Hernández, L ^{[1
]}

Pötscher, T ^{[1
]}

Dörrer, L ^{[1
]}

机构：

[1] Infineon Technol Design Ctr Austria, Villach, Austria

来源：

ESSCIRC 2003: PROCEEDINGS OF THE 29TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSCIRC.2003.1257115

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A wide bandwidth continuous time Sigma-Delta ADC implemented in a 0.13 mum CMOS technology is introduced. Active blocks are composed of regular threshold voltage devices only. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The 4(th)-order architecture uses an OpAmp-RC based loop filter and a 4 bit internal quantizer. Operated at 300 MHz clock frequency, the converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70mW operated from a 1.5V supply.

引用

页码：233 / 236

页数：4

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