A-86.88 dBc/Hz @ 1MHz K-band fractional-N frequency synthesizer in 90-nm CMOS technology

被引：1

作者：

Wang Zhengchen ^{[1
]}

Wu Zhaobo ^{[1
]}

Wang Xinghua ^{[1
]}

机构：

[1] Beijing Silicon SoC Engn Res Ctr, Beijing Inst Technol, Sch Informat & Elect, Beijing 100081, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 02期

基金：

中国国家自然科学基金;

关键词：

frequency synthesizer; phase noise; charge pump; MMD; retime technique; DIFFERENTIAL CHARGE PUMP; DESIGN;

D O I：

10.1587/elex.15.20171063

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Through 90-nm CMOS technology, a K-band fractional-N frequency synthesizer has been designed. This paper proposes a new analysis to evaluate the noise current of the charge pump in fractional-N frequency synthesizer. It also designs an improved charge pump (CP). In addition, it also presents the multi-modulus divider (MMD) by the retime technique. The measured phase noise achieves -93.5 dBc/Hz and -86.88 dBc/Hz for integer-N and fractional-N modes at 1MHz offset, respectively. The in-band phase noise performance can be improved about 20 dB by the retime technique. -54.63 dBc and -50.7 dBc reference spurs are respectively revealed by the spectrum for integer-N and fractional-N modes.

引用

页数：11

共 14 条

[11] A 1.5-2.56-GHz TDC-Assisted Fast-Locking Wideband Fractional-N CPPLL With Phase Noise of $-$ 138 dBc/Hz at 1-MHz Offset Frequency
Xiang, Ruiyong
Lu, Yixing
Luo, Xiao
Wang, Sifan
Zhang, Bodong
Shu, Shengpeng
Feng, Haigang
IEEE MICROWAVE AND WIRELESS TECHNOLOGY LETTERS, 2024, 34 (09): : 1111 - 1114
[12] A 36.3-to-38.2GHz-216dBc/Hz2 40nm CMOS Fractional-N FMCW Chirp Synthesizer PLL with a Continuous-Time Bandpass Delta-Sigma Time-to-Digital Converter
Weyer, Daniel
Dayanik, M. Batuhan
Jang, Sunmin
Flynn, Michael P.
2018 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - (ISSCC), 2018, : 250 - +
[13] 8 GHz, 20mW, fast locking, fractional-N frequency synthesizer with optimized 3rd order, 3/5-bit IIR and 3rd order 3-bit FIR noise shapers in 90nm CMOS
Ravi, A
Bishop, RE
Carley, LR
Soumyanath, K
PROCEEDINGS OF THE IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2004, : 625 - 628
[14] A X-band frequency synthesizer with 2-bit control mode is implemented in standard 0.18-μm 1P6M CMOS process. A cascoded topology of voltage control oscillator (VCO) and first stage current mode logic (CML) divider is adopted for current reuse, low power, and robust tracking between VCO and the frequency divider. The measured in-band phase noise of the synthesizer is-75.06 dBc/Hz at a frequency offset of 100 kHz and out-of-band phase noise is-119.8 dBc/Hz at a frequency offset of 10 MHz. The total power consumption is 36.75 mW. The chip size is 0.745 x 0.76mm2.
Tsai, Jeng-Han
Chao, Chia-Hsiang
Shih, Hung-Da
2012 ASIA-PACIFIC MICROWAVE CONFERENCE (APMC 2012), 2012, : 1226 - 1228

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