A new main diagonal redirection systolic tridiagonal linear system solver

The VLSI systolic processor array introduced herein implements a new Main Diagonal Redirection (MDR) linear system solver using an area-efficient fast elimination scheme. An alternative architectural design is also proposed which consists of modified systolic cells and leads to a slightly faster MDR linear system solver. The generalization of this alternative MDR approach follows, for multiple pipes arrangements on a 3D Mesh(d) architecture.