A Low Power 0.18-μm CMOS Phase Frequency Detector for High Speed PLL

This paper presents a modified high speed CMOS dynamic phase frequency detector (PFD) for high frequency phase-locked loop (PLL). Design miniaturizations in downscaling CMOS process lead to circuit malfunction due to intrinsic effects and many other reasons. To ensure main characteristics of the PFD are preserved, the proposed dynamic PFD uses 18 transistors operated with 1.2 V power supply. The performance of the design is focused on power supply, power dissipation, wide input frequency range, dead zone size and active layout area. The circuit is designed in 0.18 mu m CMOS process using Mentor Graphics environment. In this paper, the dynamic PFD dissipates 59 pW of total power when reference input frequency clock operates at 50 MHz and feedback input frequency clock operates up to 4 GHz. The dead zone has been eliminated. The simulation results show that the circuit offered an alternative for any high speed and low power PLL applications.