A 300 nW, 15 ppm/°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

被引：283
|
作者：
Ueno, Ken [1 ]
Hirose, Tetsuya [2 ]
Asai, Tetsuya [1 ]
Amemiya, Yoshihito [1 ]
机构：
[1] Hokkaido Univ, Dept Elect Engn, Sapporo, Hokkaido 0600814, Japan
[2] Kobe Univ, Dept Elect & Elect Engn, Kobe, Hyogo 6578501, Japan
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 07期
关键词：
CMOS; voltage reference; ultra-low power; subthreshold; weak inversion; process variation; die-to-die variation; power-aware LSIs; SUB-1-V; SENSOR; IMPACT;
D O I：
10.1109/JSSC.2009.2021922
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low-power CMOS voltage reference was developed using a 0.35 mu m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degrees C at best and 15 ppm/degrees C on average, in a range from -20 to 80 degrees C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 mu W at 80 degrees C. The chip area was 0.05 mm(2). Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
引用
收藏
页码：2047 / 2054
页数：8
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