ESD study on a-IGZO TFT device architectures

被引：0
|
作者：
Simicic, Marko [1 ]
Hellings, Geert [1 ]
Chen, Shih-Hung [1 ]
Myny, Kris [1 ]
Linten, Dimitri [1 ]
机构：
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
来源：
2018 40TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2018年
基金：
欧洲研究理事会;
关键词：
INTEGRATED-CIRCUITS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The indium-gallium-zinc-oxide (IGZO) thin-film-transistor (TFT) technology offers to manufacture transistors on large and flexible substrates at low processing temperatures and at a low cost. However, optimization of ESD protection devices in this technology has not been thoroughly investigated. This paper analyzes the ESD performance of three different TFT device architectures.
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页数：7
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