A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters

This paper presents a highly digital calibration technique suitable for high-speed digital-to-analog converters (DACs). The proposed calibration method does not require an adjustment of on-chip analog voltages and can therefore be a favorable method in a deeply scaled nanometer process. The calibration utilizes that adding several redundant unit current cells to predetermined weight groups can be achieved with low hardware overhead, and choosing the best subset out of multitude of combinations leads to accuracy improvement. This paper proposes a two-step coarse-fine algorithm to choose the best subset for weight groups and analyzes the design tradeoff between the amount of redundancy and the expected yield via numerical simulations. To verify the proposed calibration method, a prototype 9-bit current-steering DAC has been implemented in 90-nm CMOS technology. The calibration algorithm is implemented as software to expedite the experiment. The measured results show that static linearity performance improves by 10.8x when the proposed calibration technique is applied. When running the DAC at 5-GS/s sampling speed, similar performance improvement has been observed, achieving peak signal-to-noise-distortion ratio of 54 dB at low frequency and 8-bit linearity when generating sinusoid up to 1 GHz.