A 1.5 V high-linearity CMOS mixer for 2.4 GHz applications

被引：0

作者：

Wei, HC ^{[1
]}

Weng, RM ^{[1
]}

Lin, KY ^{[1
]}

机构：

[1] Natl Dong Hwa Univ, Dept Elect Engn, Hualien, Taiwan

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A folded-cascode mixer with a modified Class-AB transconductor for 2.4 GHz ISM band applications is presented in this paper. The mixer is composed of a modified Class-AB transconductor and a low-voltage design technique. The proposed architecture improves the performance of linearity in the RF front-end. Simulation results for the proposed mixer using tsme 0.18 mum Mixed Signal CMOS process are: input 1-dB compression point (P-1dB) -1.15 dBm, input third-order intercept point (IIP3) 11 dBm, power conversion gain 1 dB, and single side-band noise figure 17.3 dB. The mixer consumes 5.86 mA of current from a 1.5 V power supply.

引用

页码：561 / 564

页数：4

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