Hierarchical simulation approaches for the design of ultra-fast amplifier circuits

The silicon-on-insulator (SOI) technology is one of the most promising technologies as the semiconductor industry shifts to 0.13mum and smaller devices. Fully depleted (FD) SOI transistors offer a nearly ideal behavior for application in analog circuits, particularly in high frequency and low power operation. In this work, the design and development of a highly efficient power amplifier circuit is investigated for SOI technology. A fully depleted NMOS SOI transistor is built and characterized, which exhibits TeraHertz cutoff frequencies. The device parameters of this transistor are then extracted to build a compact circuit model for use in the PSPICE circuit simulator. Finally, a low power and high frequency class E power amplifier is designed based on the SOI transistor, and a full analysis of the performance compared to bulk Si technology is performed.