Gate-to-drain capacitance as a monitor for hot-carrier degradation in submicrometer MOSFET's

Determined by injecting a small sc signal at the drain and measuring the resulting current at the gate, the gate-to-drain capacitance is given by the integral of the signal potential distribution in the MOSFET channel in strong inversion. Localized trapped charges in the gate oxide distort an otherwise linear potential distribution. This gives rise to a simple geometric interpretation, allowing the polarity of the net charge, and the major degradation mechanisms to be identified. The differential capacitance, obtained from the difference in the gate capacitance before and after stress, provides evidence of the amphoteric nature of the generated interface traps. The high sensitivity of the monitor is demonstrated through capacitance data from both NMOSFET's and PMOSFET's, stressed under different conditions. Measured results are in excellent agreement with simulations, and compare well with data from charge pumping current.